UT-LCA / ML4Accel-Dataset

Dataset for ML-guided Accelerator Design

UT-LCA
UT-LCA
Date Created 2022-11-07 (2 years ago)
Commits 174 (last one about a month ago)
Stargazers 33 (0 this week)
Watchers 5 (0 this week)
Forks 4
License unknown
Ranking

RepositoryStats indexes 595,856 repositories, of these UT-LCA/ML4Accel-Dataset is ranked #555,948 (7th percentile) for total stargazers, and #335,688 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #515/563.

UT-LCA/ML4Accel-Dataset is also tagged with popular topics, for these it's ranked: verilog (#277/289),  hls (#243/252)

Other Information

UT-LCA/ML4Accel-Dataset has Github issues enabled, there are 2 open issues and 0 closed issues.

All Topics
hls rtl machine verilog

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Recent Commit History

174 commits on the default branch (main) since jan '22

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The primary language is Verilog but there's also others...

updated: 2024-12-13 @ 02:40am, id: 563042873 / R_kgDOIY9aOQ