verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

Date Created 2015-06-26 (9 years ago)
Commits 21,408 (last one 16 hours ago)
Stargazers 1,011 (0 this week)
Watchers 67 (0 this week)
Forks 391
License other
Ranking

RepositoryStats indexes 579,238 repositories, of these verilog-to-routing/vtr-verilog-to-routing is ranked #49,962 (91st percentile) for total stargazers, and #29,319 for total watchers. Github reports the primary language for this repository as C++, for repositories using this language it is ranked #2,667/31,015.

verilog-to-routing/vtr-verilog-to-routing is also tagged with popular topics, for these it's ranked: fpga (#36/474),  verilog (#27/279),  cad (#25/179),  eda (#21/137)

Other Information

verilog-to-routing/vtr-verilog-to-routing has 62 open pull requests on Github, 1,434 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 423 open issues and 598 closed issues.

There have been 5 releases, the latest one was published on 2020-03-24 (4 years ago) with the name VTR 8.0.0.

Homepage URL: https://verilogtorouting.org

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Recent Commit History

6,602 commits on the default branch (master) since jan '22

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Languages

The primary language is C++ but there's also others...

updated: 2024-11-06 @ 09:42pm, id: 38118370 / R_kgDOAkWj4g