damdoy / ice40_ultraplus_examples

Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation

Date Created 2019-01-23 (5 years ago)

Commits 35 (last one 2 years ago)

Stargazers 243 (1 this week)

Watchers 11 (0 this week)

Forks 44

License mpl-2.0

Ranking

RepositoryStats indexes 565,279 repositories, of these damdoy/ice40_ultraplus_examples is ranked #152,089 (73rd percentile) for total stargazers, and #188,879 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #94/505.

damdoy/ice40_ultraplus_examples is also tagged with popular topics, for these it's ranked: fpga (#124/462), verilog (#86/272), risc-v (#80/253)

Other Information

damdoy/ice40_ultraplus_examples has 1 open pull request on Github, 1 pull request has been merged over the lifetime of the repository.

Github issues are enabled, there are 5 open issues and 4 closed issues.

All Topics

fpga ice40 risc-v verilog

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Github watchers over time, collection started in '23

Recent Commit History

1 commits on the default branch (master) since jan '22

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Languages

The primary language is Verilog but there's also others...

updated: 2024-09-27 @ 03:54pm, id: 167263918 / R_kgDOCfg-rg