hell03end / verilog-uart

Simple 8-bit UART realization on Verilog HDL.

hell03end
hell03end
Date Created 2018-06-03 (6 years ago)
Commits 5 (last one 4 years ago)
Stargazers 101 (0 this week)
Watchers 1 (0 this week)
Forks 19
License mit
This repository has been archived on Github
Ranking

RepositoryStats indexes 630,459 repositories, of these hell03end/verilog-uart is ranked #304,205 (52nd percentile) for total stargazers, and #555,722 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #248/615.

hell03end/verilog-uart is also tagged with popular topics, for these it's ranked: fpga (#270/515),  verilog (#166/307)

Other Information

hell03end/verilog-uart has 1 open pull request on Github, 0 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 4 open issues and 0 closed issues.

All Topics
hdl fpga uart quartus verilog

Star History

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Recent Commit History

0 commits on the default branch (master) since jan '22

Inactive

No recent commits to this repository

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Commits to the default branch (master) per year

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Issue History

Total Issues
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Closed Issues
443.53.5332.52.5221.51.5110.50.50020192019202020202021202120222022202320232024202420252025

Languages

The primary language is Verilog but there's also others...

VerilogVerilogSystemVerilogSystemVerilog

updated: 2025-03-14 @ 09:30am, id: 135932086 / R_kgDOCBootg