someone755 / ddr3-controller

A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs

someone755
someone755
Date Created 2022-07-09 (2 years ago)
Commits 15 (last one 2 years ago)
Stargazers 67 (0 this week)
Watchers 3 (0 this week)
Forks 11
License unknown
Ranking

RepositoryStats indexes 635,689 repositories, of these someone755/ddr3-controller is ranked #404,743 (36th percentile) for total stargazers, and #419,275 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #339/626.

someone755/ddr3-controller is also tagged with popular topics, for these it's ranked: fpga (#361/520),  verilog (#216/310)

Other Information

someone755/ddr3-controller has Github issues enabled, there are 2 open issues and 2 closed issues.

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

665.55.5554.54.5443.53.53320232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Recent Commit History

15 commits on the default branch (master) since jan '22

1616141412121010886644220020232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Yearly Commits

Commits to the default branch (master) per year

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Issue History

Total Issues
Open Issues
Closed Issues
443.53.5332.52.5221.51.5110.50.50020232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Languages

The primary language is Verilog but there's also others...

VerilogVerilogSystemVerilogSystemVerilog

updated: 2025-03-27 @ 06:59pm, id: 512067848 / R_kgDOHoWJCA