WangXuan95 / FPGA-SHA-Family

Verilog implementation of SHA1/SHA224/SHA256/SHA384/SHA512. 使用Verilog实现的SHA1/SHA224/SHA256/SHA384/SHA512计算器。

Date Created 2020-09-01 (4 years ago)

Commits 11 (last one about a year ago)

Stargazers 61 (0 this week)

Watchers 5 (0 this week)

Forks 16

License gpl-3.0

Ranking

RepositoryStats indexes 584,353 repositories, of these WangXuan95/FPGA-SHA-Family is ranked #405,493 (31st percentile) for total stargazers, and #332,313 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #335/535.

WangXuan95/FPGA-SHA-Family is also tagged with popular topics, for these it's ranked: fpga (#355/478), verilog (#216/282)

Other Information

Homepage URL: https://gitee.com/wangxuan95/FPGA-SHA-Family

All Topics

rtl sha fpga sha1 sha224 sha256 sha384 sha512 verilog systemverilog

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

8 commits on the default branch (master) since jan '22

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Issue History

No issues have been posted

Languages

The primary language is Verilog but there's also others...

updated: 2024-11-13 @ 11:48am, id: 292003322 / R_kgDOEWed-g