WangXuan95 / FPGA-SHA-Family

Verilog implementation of SHA1/SHA224/SHA256/SHA384/SHA512. 使用Verilog实现的SHA1/SHA224/SHA256/SHA384/SHA512计算器。

Date Created 2020-09-01 (4 years ago)

Commits 11 (last one about a year ago)

Stargazers 62 (0 this week)

Watchers 5 (0 this week)

Forks 16

License gpl-3.0

Ranking

RepositoryStats indexes 595,856 repositories, of these WangXuan95/FPGA-SHA-Family is ranked #406,724 (32nd percentile) for total stargazers, and #335,688 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #338/563.

WangXuan95/FPGA-SHA-Family is also tagged with popular topics, for these it's ranked: fpga (#356/488), verilog (#215/289)

Other Information

Homepage URL: https://gitee.com/wangxuan95/FPGA-SHA-Family

All Topics

rtl sha fpga sha1 sha224 sha256 sha384 sha512 verilog systemverilog

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

8 commits on the default branch (master) since jan '22

Yearly Commits

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Issue History

No issues have been posted

Languages

The primary language is Verilog but there's also others...

updated: 2024-12-04 @ 12:53pm, id: 292003322 / R_kgDOEWed-g