Trending repositories for topic risc-v

Speech-to-text, text-to-speech, speaker diarization, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, Raspberry Pi, RISC-V, x86_64 ser...

Your Gateway to Embedded Software Development Excellence :alien:

The RISC-V Virtual Machine

:stars: List of software (HW interfaces, libs, protocols, etc) specifically suitable for resource-constrained Embedded Systems (low-memory and low-power) like 8-bit, 16-bit and 32-bit microcontrollers...

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

A fully compliant RISC-V computer made inside the game Terraria

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.

Bao, a Lightweight Static Partitioning Hypervisor

RARS -- RISC-V Assembler and Runtime Simulator

Open-source high-performance RISC-V processor

RT-Thread is an open source IoT Real-Time Operating System (RTOS).

A matrix extension proposal for AI applications under RISC-V architecture

Chisel RISC-V Vector 1.0 Implementation

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

RiVEC Bencmark Suite

Collection of various development boards for microcontrollers (e.g., CH55x, CH32, PY32, STC8, STM32) and accompanying example software.

A simple superscalar out-of-order RISC-V microprocessor

RISC-V Virtual Machine

RISC-V CPU Core

RISC-V CPU simulator for education purposes

Chisel RISC-V Vector 1.0 Implementation

A matrix extension proposal for AI applications under RISC-V architecture

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

RiVEC Bencmark Suite

Collection of various development boards for microcontrollers (e.g., CH55x, CH32, PY32, STC8, STM32) and accompanying example software.

A simple superscalar out-of-order RISC-V microprocessor

The RISC-V Virtual Machine

Bao, a Lightweight Static Partitioning Hypervisor

RISC-V Virtual Machine

Speech-to-text, text-to-speech, speaker diarization, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, Raspberry Pi, RISC-V, x86_64 ser...

:stars: List of software (HW interfaces, libs, protocols, etc) specifically suitable for resource-constrained Embedded Systems (low-memory and low-power) like 8-bit, 16-bit and 32-bit microcontrollers...

RISC-V CPU Core

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

RISC-V CPU simulator for education purposes

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

RARS -- RISC-V Assembler and Runtime Simulator

PLCT Lab ❤️ Interns!

A book about how to write OS kernels in Rust easily.

SERV - The SErial RISC-V CPU

:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Speech-to-text, text-to-speech, speaker diarization, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, Raspberry Pi, RISC-V, x86_64 ser...

Your Gateway to Embedded Software Development Excellence :alien:

The RISC-V Virtual Machine

:stars: List of software (HW interfaces, libs, protocols, etc) specifically suitable for resource-constrained Embedded Systems (low-memory and low-power) like 8-bit, 16-bit and 32-bit microcontrollers...

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

A fully compliant RISC-V computer made inside the game Terraria

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.

Bao, a Lightweight Static Partitioning Hypervisor

RARS -- RISC-V Assembler and Runtime Simulator

Open-source high-performance RISC-V processor

RT-Thread is an open source IoT Real-Time Operating System (RTOS).

A matrix extension proposal for AI applications under RISC-V architecture

Chisel RISC-V Vector 1.0 Implementation

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

RiVEC Bencmark Suite

Collection of various development boards for microcontrollers (e.g., CH55x, CH32, PY32, STC8, STM32) and accompanying example software.

A simple superscalar out-of-order RISC-V microprocessor

RISC-V Virtual Machine

RISC-V CPU Core

RISC-V CPU simulator for education purposes

Chisel RISC-V Vector 1.0 Implementation

A matrix extension proposal for AI applications under RISC-V architecture

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

RiVEC Bencmark Suite

Collection of various development boards for microcontrollers (e.g., CH55x, CH32, PY32, STC8, STM32) and accompanying example software.

A simple superscalar out-of-order RISC-V microprocessor

The RISC-V Virtual Machine

Bao, a Lightweight Static Partitioning Hypervisor

RISC-V Virtual Machine

Speech-to-text, text-to-speech, speaker diarization, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, Raspberry Pi, RISC-V, x86_64 ser...

:stars: List of software (HW interfaces, libs, protocols, etc) specifically suitable for resource-constrained Embedded Systems (low-memory and low-power) like 8-bit, 16-bit and 32-bit microcontrollers...

RISC-V CPU Core

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

RISC-V CPU simulator for education purposes

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

RARS -- RISC-V Assembler and Runtime Simulator

PLCT Lab ❤️ Interns!

A book about how to write OS kernels in Rust easily.

SERV - The SErial RISC-V CPU

:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Speech-to-text, text-to-speech, speaker diarization, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, Raspberry Pi, RISC-V, x86_64 ser...

RT-Thread is an open source IoT Real-Time Operating System (RTOS).

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.

Open-source high-performance RISC-V processor

Your Gateway to Embedded Software Development Excellence :alien:

A book about how to write OS kernels in Rust easily.

A secure embedded operating system for microcontrollers

Lightweight justice for your single-board computer!

The Ultra-Low Power RISC-V Core

The official repository for the gem5 computer-system architecture simulator.

A graphical processor simulator and assembly editor for the RISC-V ISA

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems

Modern, advanced, portable, multiprotocol bootloader and boot manager.

Let's write an OS which can run on RISC-V in Rust from scratch!

3-stage RV32IMACZb* processor with debug

RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.

Unicode routines (UTF8, UTF16, UTF32) and Base64: billions of characters per second using SSE2, AVX2, NEON, AVX-512, RISC-V Vector Extension. Part of Node.js, WebKit/Safari, Ladybird, Cloudflare Worke...

Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards

The RISC-V Virtual Machine

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

A concise explanation of Rust types and Memory Layout.

Light weight hypervisor for RISC-V H-extension.

A simple superscalar out-of-order RISC-V microprocessor

a game where you're given a potato and your job is to implement a firmware for it

RISC-V machine code monitor

RiVEC Bencmark Suite

Open source ISS and logic RISC-V 32 bit project

Chisel RISC-V Vector 1.0 Implementation

RISC-V Virtual Machine

x86-64, ARM, and RVV intrinsics viewer

A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education and research.

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

Speech-to-text, text-to-speech, speaker diarization, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, Raspberry Pi, RISC-V, x86_64 ser...

Build .NET SDK for RISC-V

A RISC-V assembler written in Lisp.

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...

Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chili-chips.xyz/open-cologne

Advanced Architecture Labs with CVA6

NixOS Running on LicheePi 4A(RISC-V)

Detect CPU features with single-file

Linux on a $0.15 RISC-V microcontroller

a game where you're given a potato and your job is to implement a firmware for it

An exquisite superscalar RV32GC processor.

USB Power Delivery Testing Device and Variable Power Supply

Emulador Genérico do Gabriel

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

Portable Digital FM Radio Receiver with RDS

Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chili-chips.xyz/open-cologne

An operating system🧑‍💻 written using C and Sage

Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"

RISC-V machine code monitor

Rust HAL crate for HPMicro's RISC-V MCUs: HPM6700/HPM6400, HPM6300, HPM6200, HPM5300, HPM6800, HPM6E00.

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...

Portable Programmable Power Supply

Build .NET SDK for RISC-V

A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave

Speech-to-text, text-to-speech, speaker diarization, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, Raspberry Pi, RISC-V, x86_64 ser...

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.

RT-Thread is an open source IoT Real-Time Operating System (RTOS).

Your Gateway to Embedded Software Development Excellence :alien:

Open-source high-performance RISC-V processor

A fully compliant RISC-V computer made inside the game Terraria

A secure embedded operating system for microcontrollers

Lightweight justice for your single-board computer!

3-stage RV32IMACZb* processor with debug

Modern, advanced, portable, multiprotocol bootloader and boot manager.

RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.

Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards

The official repository for the gem5 computer-system architecture simulator.

A self-hosting and educational C optimizing compiler

Let's write an OS which can run on RISC-V in Rust from scratch!

A graphical processor simulator and assembly editor for the RISC-V ISA

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Reko is a binary decompiler.

Detect CPU features with single-file

USB Power Delivery Testing Device and Variable Power Supply

a game where you're given a potato and your job is to implement a firmware for it

Speech-to-text, text-to-speech, speaker diarization, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, Raspberry Pi, RISC-V, x86_64 ser...

3-stage RV32IMACZb* processor with debug

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

Chisel RISC-V Vector 1.0 Implementation

A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code

RISC-V Virtual Machine

Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...

RISC-V Embedded Processor for Approximate Computing

A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave

RISC-V Nox core

x86-64, ARM, and RVV intrinsics viewer

Templates for bare-metal firmware development for some entry-level microcontrollers

RISC-V CPU simulator for education purposes

Collection of various development boards for microcontrollers (e.g., CH55x, CH32, PY32, STC8, STM32) and accompanying example software.

A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)

Handheld RISC-V Mini Game Console with OLED Display