Trending repositories for topic risc-v
Speech-to-text, text-to-speech, and speaker recongition using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, Raspberry Pi, RISC-V, x86_64 servers,...
A fully compliant RISC-V computer made inside the game Terraria
RT-Thread is an open source IoT real-time operating system (RTOS).
Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems
RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.
The official repository for the gem5 computer-system architecture simulator.
Your Gateway to Embedded Software Development Excellence :alien:
Let's write an OS which can run on RISC-V in Rust from scratch!
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Open source RISC-V microcontroller unit for FPGAs written in Verilog
Speech-to-text, text-to-speech, and speaker recongition using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, Raspberry Pi, RISC-V, x86_64 servers,...
Open source RISC-V microcontroller unit for FPGAs written in Verilog
A fully compliant RISC-V computer made inside the game Terraria
PlatformIO platform for CH32V RISC-V chips (CH32V003, CH32V103, CH32V20x, CH32V30x, CH32X035) and CH56x, CH57x, CH58x, CH59x
A 256-RISC-V-core system with low-latency access into shared L1 memory.
Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems
The official repository for the gem5 computer-system architecture simulator.
RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.
Let's write an OS which can run on RISC-V in Rust from scratch!
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Speech-to-text, text-to-speech, and speaker recongition using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, Raspberry Pi, RISC-V, x86_64 servers,...
A fully compliant RISC-V computer made inside the game Terraria
RT-Thread is an open source IoT real-time operating system (RTOS).
RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.
The official repository for the gem5 computer-system architecture simulator.
Your Gateway to Embedded Software Development Excellence :alien:
Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Let's write an OS which can run on RISC-V in Rust from scratch!
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Speech-to-text, text-to-speech, and speaker recongition using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, Raspberry Pi, RISC-V, x86_64 servers,...
A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one
Open source RISC-V microcontroller unit for FPGAs written in Verilog
PlatformIO platform for CH32V RISC-V chips (CH32V003, CH32V103, CH32V20x, CH32V30x, CH32X035) and CH56x, CH57x, CH58x, CH59x
A fully compliant RISC-V computer made inside the game Terraria
A 256-RISC-V-core system with low-latency access into shared L1 memory.
RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.
Speech-to-text, text-to-speech, and speaker recongition using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, Raspberry Pi, RISC-V, x86_64 servers,...
RT-Thread is an open source IoT real-time operating system (RTOS).
A fully compliant RISC-V computer made inside the game Terraria
Your Gateway to Embedded Software Development Excellence :alien:
RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.
The official repository for the gem5 computer-system architecture simulator.
Let's write an OS which can run on RISC-V in Rust from scratch!
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Speech-to-text, text-to-speech, and speaker recongition using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, Raspberry Pi, RISC-V, x86_64 servers,...
A portable RISC-V emulator working in instruction-interpreting way. Common SoC peripherals are emulated. Support running mainline Linux. 可移植的 RISC-V 解释执行模拟器。模拟了常见的SoC外设，并支持运行主线Linux。
A matrix extension proposal for AI applications under RISC-V architecture
A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one
Templates for bare-metal firmware development for some entry-level microcontrollers
PlatformIO platform for CH32V RISC-V chips (CH32V003, CH32V103, CH32V20x, CH32V30x, CH32X035) and CH56x, CH57x, CH58x, CH59x
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSVs) to interoperate with one another by providing expectations f...
An open source WCH-Link library/command line tool written in Rust.
A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
[Tested successfully] Linux on Arduino UNO / atmega328p port of mini-rv32ima. Let's run Linux on the world's worst Linux PC (and beat Dmitry Grinberg)
Lower level assembly and C baremetal programming on RISC-V CPUs. Source code listings from the C-Ninja, in Pyjama! book.
A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
A portable RISC-V emulator working in instruction-interpreting way. Common SoC peripherals are emulated. Support running mainline Linux. 可移植的 RISC-V 解释执行模拟器。模拟了常见的SoC外设，并支持运行主线Linux。
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
Templates for bare-metal firmware development for some entry-level microcontrollers
SharpRISCV is an implementation of RISC-V assembly in C#. First RISC V Assembly that build windows executable file
A fully compliant RISC-V computer made inside the game Terraria
Speech-to-text, text-to-speech, and speaker recongition using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, Raspberry Pi, RISC-V, x86_64 servers,...
RT-Thread is an open source IoT real-time operating system (RTOS).
Your Gateway to Embedded Software Development Excellence :alien:
RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.
Let's write an OS which can run on RISC-V in Rust from scratch!
The official repository for the gem5 computer-system architecture simulator.
:stars: List of software (HW interfaces, libs, protocols, etc) specifically suitable for resource-constrained Embedded Systems (low-memory and low-power) like 8-bit, 16-bit and 32-bit microcontrollers...
A graphical processor simulator and assembly editor for the RISC-V ISA
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
A fully compliant RISC-V computer made inside the game Terraria
USB Power Delivery Testing Device and Variable Power Supply
Speech-to-text, text-to-speech, and speaker recongition using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, Raspberry Pi, RISC-V, x86_64 servers,...
Collection of various development boards for microcontrollers (e.g., CH55x, CH32, PY32, STC8, STM32) and accompanying example software.
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSVs) to interoperate with one another by providing expectations f...
PlatformIO platform for CH32V RISC-V chips (CH32V003, CH32V103, CH32V20x, CH32V30x, CH32X035) and CH56x, CH57x, CH58x, CH59x
A matrix extension proposal for AI applications under RISC-V architecture
:stars: List of software (HW interfaces, libs, protocols, etc) specifically suitable for resource-constrained Embedded Systems (low-memory and low-power) like 8-bit, 16-bit and 32-bit microcontrollers...