Trending repositories for topic risc-v
Speech-to-text, text-to-speech, speaker diarization, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, HarmonyOS, Raspberry Pi, RISC-V,...
A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.
Your Gateway to Embedded Software Development Excellence :alien:
Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
RT-Thread is an open source IoT Real-Time Operating System (RTOS).
RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.
a game where you're given a potato and your job is to implement a firmware for it
Unicode routines (UTF8, UTF16, UTF32) and Base64: billions of characters per second using SSE2, AVX2, NEON, AVX-512, RISC-V Vector Extension, LoongArch64. Part of Node.js, WebKit/Safari, Ladybird, Chr...
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
:stars: List of software (HW interfaces, libs, protocols, etc) specifically suitable for resource-constrained Embedded Systems (low-memory and low-power) like 8-bit, 16-bit and 32-bit microcontrollers...
a game where you're given a potato and your job is to implement a firmware for it
Speech-to-text, text-to-speech, speaker diarization, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, HarmonyOS, Raspberry Pi, RISC-V,...
Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
Unicode routines (UTF8, UTF16, UTF32) and Base64: billions of characters per second using SSE2, AVX2, NEON, AVX-512, RISC-V Vector Extension, LoongArch64. Part of Node.js, WebKit/Safari, Ladybird, Chr...
:stars: List of software (HW interfaces, libs, protocols, etc) specifically suitable for resource-constrained Embedded Systems (low-memory and low-power) like 8-bit, 16-bit and 32-bit microcontrollers...
Your Gateway to Embedded Software Development Excellence :alien:
A book about how to write OS kernels in Rust easily.
Speech-to-text, text-to-speech, speaker diarization, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, HarmonyOS, Raspberry Pi, RISC-V,...
Your Gateway to Embedded Software Development Excellence :alien:
Unicode routines (UTF8, UTF16, UTF32) and Base64: billions of characters per second using SSE2, AVX2, NEON, AVX-512, RISC-V Vector Extension, LoongArch64. Part of Node.js, WebKit/Safari, Ladybird, Chr...
RT-Thread is an open source IoT Real-Time Operating System (RTOS).
A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.
Modern, advanced, portable, multiprotocol bootloader and boot manager.
A graphical processor simulator and assembly editor for the RISC-V ISA
A fully compliant RISC-V computer made inside the game Terraria
RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.
Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Minimal assembler and ecosystem for bare-metal RISC-V development
General purpose operating system targeting standard desktops and laptops.
a game where you're given a potato and your job is to implement a firmware for it
Unicode routines (UTF8, UTF16, UTF32) and Base64: billions of characters per second using SSE2, AVX2, NEON, AVX-512, RISC-V Vector Extension, LoongArch64. Part of Node.js, WebKit/Safari, Ladybird, Chr...
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
Speech-to-text, text-to-speech, speaker diarization, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, HarmonyOS, Raspberry Pi, RISC-V,...
Collection of various development boards for microcontrollers (e.g., CH55x, CH32, PY32, STC8, STM32) and accompanying example software.
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems
A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.
Speech-to-text, text-to-speech, speaker diarization, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, HarmonyOS, Raspberry Pi, RISC-V,...
RT-Thread is an open source IoT Real-Time Operating System (RTOS).
Your Gateway to Embedded Software Development Excellence :alien:
a game where you're given a potato and your job is to implement a firmware for it
A fully compliant RISC-V computer made inside the game Terraria
Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards
The official repository for the gem5 computer-system architecture simulator.
RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.
Unicode routines (UTF8, UTF16, UTF32) and Base64: billions of characters per second using SSE2, AVX2, NEON, AVX-512, RISC-V Vector Extension, LoongArch64. Part of Node.js, WebKit/Safari, Ladybird, Chr...
Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
A graphical processor simulator and assembly editor for the RISC-V ISA
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
a game where you're given a potato and your job is to implement a firmware for it
Yet another RISC-V Simulator on the web, running on Webassembly! https://riscv.vercel.app/
A POSIX RISC-V OS kernel written in C23, featuring preemptive priority scheduling, virtual memory, tiered allocators, time management, modular device drivers, with support for ELF and VirtIO-GPU.
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...
Tool for converting PyTorch models into raw C codes with minimal dependency and some performance optimizations.
A matrix extension proposal for AI applications under RISC-V architecture
Templates for bare-metal firmware development for some entry-level microcontrollers
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
General purpose operating system targeting standard desktops and laptops.
Speech-to-text, text-to-speech, speaker diarization, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, HarmonyOS, Raspberry Pi, RISC-V,...
PlatformIO platform for CH32V RISC-V chips (CH32V003, CH32V103, CH32V20x, CH32V30x, CH32X035) and CH56x, CH57x, CH58x, CH59x
A concise explanation of Rust types and Memory Layout.
The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSVs) to interoperate with one another by providing expectations f...
An open source WCH-Link library/command line tool written in Rust.
a game where you're given a potato and your job is to implement a firmware for it
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https://na...
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...
Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
A POSIX RISC-V OS kernel written in C23, featuring preemptive priority scheduling, virtual memory, tiered allocators, time management, modular device drivers, with support for ELF and VirtIO-GPU.
Rust HAL crate for HPMicro's RISC-V MCUs: HPM6700/HPM6400, HPM6300, HPM6200, HPM5300, HPM6800, HPM6E00.
A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
Speech-to-text, text-to-speech, speaker diarization, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, HarmonyOS, Raspberry Pi, RISC-V,...
A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.
RT-Thread is an open source IoT Real-Time Operating System (RTOS).
Your Gateway to Embedded Software Development Excellence :alien:
A fully compliant RISC-V computer made inside the game Terraria
Modern, advanced, portable, multiprotocol bootloader and boot manager.
Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards
RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.
The official repository for the gem5 computer-system architecture simulator.
Let's write an OS which can run on RISC-V in Rust from scratch!
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
A graphical processor simulator and assembly editor for the RISC-V ISA
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Unicode routines (UTF8, UTF16, UTF32) and Base64: billions of characters per second using SSE2, AVX2, NEON, AVX-512, RISC-V Vector Extension, LoongArch64. Part of Node.js, WebKit/Safari, Ladybird, Chr...
a game where you're given a potato and your job is to implement a firmware for it
USB Power Delivery Testing Device and Variable Power Supply
Speech-to-text, text-to-speech, speaker diarization, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, HarmonyOS, Raspberry Pi, RISC-V,...
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
RISC-V Embedded Processor for Approximate Computing
Templates for bare-metal firmware development for some entry-level microcontrollers
Yet another RISC-V Simulator on the web, running on Webassembly! https://riscv.vercel.app/