Trending repositories for topic risc-v

Speech-to-text, text-to-speech, speaker diarization, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, Raspberry Pi, RISC-V, x86_64 ser...

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.

RT-Thread is an open source IoT Real-Time Operating System (RTOS).

Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards

The official repository for the gem5 computer-system architecture simulator.

A graphical processor simulator and assembly editor for the RISC-V ISA

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems

Your Gateway to Embedded Software Development Excellence :alien:

Modern, advanced, portable, multiprotocol bootloader and boot manager.

Unicode routines (UTF8, UTF16, UTF32) and Base64: billions of characters per second using SSE2, AVX2, NEON, AVX-512, RISC-V Vector Extension. Part of Node.js, WebKit/Safari, Ladybird, Cloudflare Worke...

Lightweight justice for your single-board computer!

Let's write an OS which can run on RISC-V in Rust from scratch!

Open-source high-performance RISC-V processor

The fastest RISC-V sandbox

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

A self-hosting and educational C optimizing compiler

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

JTAG probe firmware

RARS -- RISC-V Assembler and Runtime Simulator

A RISC-V assembler written in Lisp.

fdtd3d is an open source 1D, 2D, 3D FDTD electromagnetics solver with MPI, OpenMP and CUDA support for x64, ARM, ARM64, RISC-V, PowerPC, Wasm architectures

Standalone C compiler for RISC-V and ARM

Speech-to-text, text-to-speech, speaker diarization, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, Raspberry Pi, RISC-V, x86_64 ser...

TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems

The fastest RISC-V sandbox

RISC-V Assembly Language Programming

Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards

JTAG probe firmware

The official repository for the gem5 computer-system architecture simulator.

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Unicode routines (UTF8, UTF16, UTF32) and Base64: billions of characters per second using SSE2, AVX2, NEON, AVX-512, RISC-V Vector Extension. Part of Node.js, WebKit/Safari, Ladybird, Cloudflare Worke...

32-bit RISC-V system on chip for iCE40 FPGAs

Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

Modern, advanced, portable, multiprotocol bootloader and boot manager.

A graphical processor simulator and assembly editor for the RISC-V ISA

RISC-V CPU simulator for education purposes

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.

Speech-to-text, text-to-speech, speaker diarization, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, Raspberry Pi, RISC-V, x86_64 ser...

RT-Thread is an open source IoT Real-Time Operating System (RTOS).

Open-source high-performance RISC-V processor

Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards

The official repository for the gem5 computer-system architecture simulator.

RISC-V CPU Core (RV32IM)

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Unicode routines (UTF8, UTF16, UTF32) and Base64: billions of characters per second using SSE2, AVX2, NEON, AVX-512, RISC-V Vector Extension. Part of Node.js, WebKit/Safari, Ladybird, Cloudflare Worke...

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Lightweight justice for your single-board computer!

RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.

Modern, advanced, portable, multiprotocol bootloader and boot manager.

A graphical processor simulator and assembly editor for the RISC-V ISA

Your Gateway to Embedded Software Development Excellence :alien:

Let's write an OS which can run on RISC-V in Rust from scratch!

The Ultra-Low Power RISC-V Core

Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

Chisel RISC-V Vector 1.0 Implementation

A RISC-V assembler written in Lisp.

Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chili-chips.xyz/open-cologne

Lower level assembly and C baremetal programming on RISC-V CPUs. Source code listings from the C-Ninja, in Pyjama! book.

RISC-V emulator in python

Collection of various development boards for microcontrollers (e.g., CH55x, CH32, PY32, STC8, STM32) and accompanying example software.

A simple RISC-V CPU written in Verilog.

Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)

fdtd3d is an open source 1D, 2D, 3D FDTD electromagnetics solver with MPI, OpenMP and CUDA support for x64, ARM, ARM64, RISC-V, PowerPC, Wasm architectures

Templates for bare-metal firmware development for some entry-level microcontrollers

Speech-to-text, text-to-speech, speaker diarization, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, Raspberry Pi, RISC-V, x86_64 ser...

32-bit RISC-V Forth for microcontrollers

Standalone C compiler for RISC-V and ARM

Handheld RISC-V Mini Game Console with OLED Display

A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code

A simple superscalar out-of-order RISC-V microprocessor

Sedna - a pure Java RISC-V emulator.

RISC-V CPU Core (RV32IM)

PlatformIO platform for CH32V RISC-V chips (CH32V003, CH32V103, CH32V20x, CH32V30x, CH32X035) and CH56x, CH57x, CH58x, CH59x

Unicode routines (UTF8, UTF16, UTF32) and Base64: billions of characters per second using SSE2, AVX2, NEON, AVX-512, RISC-V Vector Extension. Part of Node.js, WebKit/Safari, Ladybird, Cloudflare Worke...

Speech-to-text, text-to-speech, speaker diarization, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, Raspberry Pi, RISC-V, x86_64 ser...

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.

RT-Thread is an open source IoT Real-Time Operating System (RTOS).

Your Gateway to Embedded Software Development Excellence :alien:

Open-source high-performance RISC-V processor

The official repository for the gem5 computer-system architecture simulator.

Lightweight justice for your single-board computer!

Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

A graphical processor simulator and assembly editor for the RISC-V ISA

A secure embedded operating system for microcontrollers

A simple superscalar out-of-order RISC-V microprocessor

RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Modern, advanced, portable, multiprotocol bootloader and boot manager.

The Ultra-Low Power RISC-V Core

RISC-V CPU Core (RV32IM)

Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

A fully compliant RISC-V computer made inside the game Terraria

A simple superscalar out-of-order RISC-V microprocessor

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...

Chisel RISC-V Vector 1.0 Implementation

Open source ISS and logic RISC-V 32 bit project

A concise explanation of Rust types and Memory Layout.

RiVEC Bencmark Suite

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

A matrix extension proposal for AI applications under RISC-V architecture

Light weight hypervisor for RISC-V H-extension.

Speech-to-text, text-to-speech, speaker diarization, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, Raspberry Pi, RISC-V, x86_64 ser...

Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)

A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code

RISC-V machine code monitor

Lower level assembly and C baremetal programming on RISC-V CPUs. Source code listings from the C-Ninja, in Pyjama! book.

RISC-V Virtual Machine

A simple RISC-V CPU written in Verilog.

A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education and research.

Templates for bare-metal firmware development for some entry-level microcontrollers

Build embedded applications with the IAR Build Tools on Docker Containers

Detect CPU features with single-file

Linux on a $0.15 RISC-V microcontroller

a game where you're given a potato and your job is to implement a firmware for it

An exquisite superscalar RV32GC processor.

USB Power Delivery Testing Device and Variable Power Supply

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

Portable Digital FM Radio Receiver with RDS

Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chili-chips.xyz/open-cologne

An operating system🧑‍💻 written using C and Sage

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...

Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"

RISC-V machine code monitor

Rust HAL crate for HPMicro's RISC-V MCUs: HPM6700/HPM6400, HPM6300, HPM6200, HPM5300, HPM6800, HPM6E00.

Portable Programmable Power Supply

Build .NET SDK for RISC-V

A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave

Speech-to-text, text-to-speech, speaker diarization, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, Raspberry Pi, RISC-V, x86_64 ser...

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.

RT-Thread is an open source IoT Real-Time Operating System (RTOS).

Your Gateway to Embedded Software Development Excellence :alien:

Open-source high-performance RISC-V processor

A secure embedded operating system for microcontrollers

A fully compliant RISC-V computer made inside the game Terraria

Lightweight justice for your single-board computer!

3-stage RV32IMACZb* processor with debug

Modern, advanced, portable, multiprotocol bootloader and boot manager.

Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards

RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.

The official repository for the gem5 computer-system architecture simulator.

A self-hosting and educational C optimizing compiler

Let's write an OS which can run on RISC-V in Rust from scratch!

A graphical processor simulator and assembly editor for the RISC-V ISA

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Reko is a binary decompiler.

Detect CPU features with single-file

USB Power Delivery Testing Device and Variable Power Supply

a game where you're given a potato and your job is to implement a firmware for it

RTOS with preemptive kernel 📺

Speech-to-text, text-to-speech, speaker diarization, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, Raspberry Pi, RISC-V, x86_64 ser...

3-stage RV32IMACZb* processor with debug

Chisel RISC-V Vector 1.0 Implementation

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...

RISC-V Virtual Machine

Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"

RISC-V Embedded Processor for Approximate Computing

A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave

RISC-V Nox core

A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code

Templates for bare-metal firmware development for some entry-level microcontrollers

RISC-V CPU simulator for education purposes

Light weight hypervisor for RISC-V H-extension.

x86-64, ARM, and RVV intrinsics viewer

A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)